1. Field of the Invention
The invention relates generally to a semiconductor structure, and more particularly to copper (Cu) interconnects embedded in the same insulating level layer with different copper grain sizes.
2. Description of the Related Art
One problem encountered in semiconductor manufacturing is the manufacture of copper (Cu) interconnects within the same insulating level layer with different Cu grain sizes. Currently, Cu interconnects formed within the same insulating level layer comprise the same Cu grain size. The limitation of a single Cu grain size for interconnects embedded within the same insulating layer is problematic because, for certain applications Cu interconnects perform more advantageously with a smaller Cu grain size, while for other applications Cu interconnects perform more advantageously with a larger Cu grain size. For example, a large Cu grain size results in lower electrical resistivity and longer electromigration lifetime, which is preferred for a high performance related application, while a small Cu grain size results in higher electrical resistivity and shorter electromigration lifetime, which is preferred for electrical-fuse related applications.
With current semiconductor manufacturing techniques to acquire Cu interconnects with Cu grain size optimized for a chosen application, multiple layers of Cu interconnects embedded within an insulating level layer must be created. Each insulating level layer will have embedded Cu interconnects with the same Cu grain size. Creation of a new layer of Cu interconnects to obtain Cu interconnects with different Cu grain sizes doubles the semiconductor processing steps. In addition, creation of a new layer of Cu interconnects with a different Cu grain size, doubles manufacturing costs.
As discussed herein above, a small Cu grain sized Cu interconnect is preferred for electrical-fuse (e-fuse) related applications. Electrically blowable fuses take advantage of the electromigration (EM) effect to open an electrical connection. During programming, voids form at a center fuse element due to high current density, and eventually create an electrically open circuit. It is also known that Cu grain size has a certain level of impact on electromigration resistance. In general, a larger Cu grain size (i.e.: closer to bamboo-type grain microstructure) leads to fewer grain boundaries that have components normal to the electron flow, and a smaller Cu grain size results in lower EM resistance because of more Cu diffusion through the grain boundaries. For e-fuse programming efficiency, a small Cu grain interconnect is ideal.
Further, as discussed herein above, a large grain sized Cu interconnect is preferred for a high performance applications. Large Cu grain size results in a Cu interconnect with lower resistivity. Big Cu grain size results in lower resistivity because there are fewer grain boundaries with a larger Cu grain size (i.e.: closer to bamboo-type grain microstructure). Grain boundaries cause electron scattering. Therefore, fewer grain boundaries results in less electron scattering, which in turn, results in less resistivity and higher conductivity. For better circuit performance with higher conductivity, a Cu interconnect with a large Cu grains is preferred.
FIG. 1 depicts prior art Cu interconnects 100a, 100b embedded in the same insulating level layer 12 with the same Cu grain size. Note that FIG. 1 depicts parallel pairs of single 10 and dual damascene 20 structures at the same insulating level layer 12. Both the single 10 and dual damascene 20 structures comprise a barrier material 14, copper seed 24, and electroplated copper 26b. Note that the electroplated copper structures 26b in 100a and 100b have the same small Cu grain size, which is evident by virtue of the multiple grain boundaries in the electroplated copper 26b depicted in FIG. 1. Therefore, as discussed herein above, the Cu interconnects 100a, 100b depicted in FIG. 1 would be ideal for an e-fuse application.
What is needed in the art are Cu interconnects embedded in the same insulating level layer with divergent Cu grain sizes, such that the Cu grain size for a given Cu interconnect enables such Cu interconnect to most efficiently perform for an intended application for such Cu interconnect without the need for duplicative semiconductor processing steps and associated costs.